1. Field of the Invention
The present invention relates generally to digital fractional-N phase lock loop, and more particularly but not exclusively to method and apparatus for reducing phase noise of digital fractional-N phase lock loop.
2. Description of Related Art
A digital PLL (phase lock loop) receives a reference clock of a first frequency and generates accordingly an output clock of a second frequency, wherein the output clock is phase-locked to the reference clock and the second frequency is N times higher than the first frequency. As depicted in FIG. 1A, a typical digital PLL 100A comprises a TDC (time-to-digital converter) 110 for measuring a time difference between the reference clock REF of the first frequency and a feedback clock FB of a third frequency and generating accordingly a time difference signal TD for representing the time difference; a digital loop filter 120 for filtering the time difference signal TD (which is a digital signal) and generating a control code C; a DCO (digitally controlled oscillator) 130 for generating the output clock OUT of the second frequency in accordance with a value of the control code C; and a divide-by-N circuit 140A for generating the feedback clock FB of the third frequency by dividing down the output clock OUT of the second frequency with a divisor value of N. The second frequency, i.e. the frequency of the output clock OUT and also the oscillation frequency of DCO 130, is controlled by the value of the control code C. In an embodiment, the frequency of the output clock OUT (i.e. the second frequency, the oscillation frequency of the DCO 130) increases (decreases) in response to an increase (decrease) of the value of the control code C. Due to the divide-by-N function of the divide-by-N circuit 140A, the second frequency is N time higher than the third frequency. When the control code C is too small (large), the second frequency will be too low (high) and accordingly the third frequency will also be too low (high). In this case, the feedback clock FB will be too slow (fast) and thus trail (lead) the reference clock REF, resulting in a positive (negative) value of the time difference signal TD, indicating a positive (negative) time difference between the reference clock REF and the feedback clock FB. The digital loop filter 130 usually includes an integration function. A positive (negative) value of the time difference signal TD leads to an increase (decrease) of the value of the control code C, thanks to the integration function of the digital loop filter 130. In this closed-loop manner, the control code C is adjusted (i.e. increased or decreased) to make the timing (i.e. frequency and phase) of the feedback clock FB tracks the timing of the reference clock REF. In a steady state where the control code C settles into a proper value, the mean value of the time difference signal TD must be zero (otherwise, the control code C will blow up and cannot be settled, thanks to the integration function of the digital loop filter 130). In the steady state, therefore, the third frequency must be equal to the first frequency, and consequently the second frequency must be N times higher than the first frequency since the second frequency is N time higher than the third frequency due to the divide-by-N divider circuit 140A.
The divide-by-N circuit 140A for the digital PLL 100A of FIG. 1A can be conveniently implemented using a divide-by-N counter if N is an integer. If N is not an integer, however, a straight implementation using a counter with a fixed divisor value will not work, since the divisor value of a counter always needs to be an integer. To implement a divide-by-N function for a non-integer N, say N=Nint+α where Nint is an integer and α is a fractional number between 0 and 1, we need to shuffle the divisor value for the counter. For example, we may shuffle the divisor value between Nint and (Nint+1); the effective divisor value will be equal to Nint+α as long as the probability of having the divisor value of (Nint+1) is α and the probability of having the divisor value of Nint is (1−α). In prior art, a delta-sigma modulator is often used to dynamically shuffle the divisor value.
By embodying the divide-by-N circuit 140A of digital PLL 100A using embodiment circuit 140B resulting in a digital fractional-N PLL 100B shown in FIG. 1B. Embodiment circuit 140B comprises: a dual-modulus divider (DMD) 150 for generating the feedback clock FB by dividing down by dividing down the output clock OUT by a divisor value of either Nint or (Nint+1), depending on a value of a binary code CARRY; a DSM (delta-sigma modulator) 160 for receiving the fractional number α and modulating it into the binary code CARRY in accordance with a timing provided by the feedback clock FB. The purpose of DSM 160 is to generate the binary code CARRY in a manner such that CARRY is either 0, with a probability of α, or 1, with a probability of (1−α), and the mean value of CARRY is equal to α. In this manner, the feedback clock FB is divided-down from the output clock OUT by a divisor value shuffled between Nint and (Nint+1) with a mean value of Nint+α.
Shuffling the divisor value for the divide-by-N circuit effectively achieves a fractional-N division. In this case, in the steady state, the mean timing difference between the reference clock REF and the feedback clock FB (i.e. the mean value of the time difference signal TD) is still zero, but the instantaneous timing difference is not zero and can be almost as large as TDCO/2, where TDCO denotes a cycle period of the output clock OUT, due to the shuffling of the divisor value between Nint and (Nint+1). The instantaneous timing difference leads to instantaneous noise in the time difference signal TD, resulting in a noise in the control code C and thus a phase noise in the output clock OUT.
Besides the phase noise due to the shuffling of the divisor value, non-idealities of the TDC 110 (of either FIG. 1A or FIG. 1B) also contribute to the phase noise in the output clock OUT. As depicted in FIG. 1C, the time difference signal TD should be proportional to the time difference between the reference clock REF and the feedback clock FB, as demonstrated by the dashed straight line 170. In practice, however, the transfer characteristics of a TDC will likely deviate from the dashed straight line 170, as exemplified by a curved line 180. The deviation from an ideal straight line effectively introduces an error into the time difference signal TD and therefore contributes to the phase noise in the output clock OUT.
What is needed is a method to cancel the phase noise caused by both the shuffling of the value of the divisor and the non-idealities of the TDC.